1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a ferroelectric memory device method thereof.
2. Background of the Related Art
A ferroelectric random access memory (FRAM) has the data processing speed as fast as a DRAM, which is widely used as a semiconductor memory device, and stores data even in a power-off state. The FRAM has a structure similar to the DRAM and employs ferroelectric as the capacitor material to use its high residual polarization characteristic. With this characteristic, the data stored in the FRAM is not erased even when electric field applied thereto is removed.
As shown in FIG. 1, a polarization induced by electric field does not disappear, even when the electric field is removed, due to existence of spontaneous polarization but remains in a specific amount (states of d and a). The states d and a correspond to data 1 and 0, respectively, for the memory device.
FIG. 2 illustrates the configuration of the unit cell of a conventional ferroelectric memory device. FIG. 3 illustrates the configuration of the cell array of the conventional ferroelectric memory device. FIG. 4 illustrates operation waveforms of the conventional ferroelectric memory device.
An ideal structure of an FRAM using a ferroelectric layer is the one which is similar to DRAM. However, it has the problem in terms of integration, which is difficult to solve if new materials for forming an electrode and barrier are not used. Such problems occur because capacitors cannot be directly formed on a silicon substrate or polysilicon layer to make the area of FRAM larger than the DRAM with the same capacitance. Furthermore, when electric field is repeatedly applied to the ferroelectric to reiterate polarization inversion, the amount of residual polarization is reduced, which results in fatigue of the thin film. Such a fatigue deteriorates the reliability of device.
The FRAM structure shown in FIG. 2 has been used with regard to such matters, including substitutes for electrode materials currently developed, integration, stability of ferroelectric thin film and operation reliability. The unit cell of the conventional FRAM consists of first and second NMOS transistors 1 and 3 whose gates are commonly connected to a word line 5, and first and second ferroelectric capacitors 2 and 4 formed using a ferroelectric material. The drain and source of the first transistor 1 are respectively connected to a bit line (Bit_n) 6 and a first node 1 (N1). The drain and source of the second transistor 3 are respectively connected to a /bit line (BitB_n) 7 and a second node 2 (N2). The electrodes of the first ferroelectric capacitor 2 are connected to the first node 1 (N1) and a cell plate line 8, and the electrodes of the second ferroelectric capacitor 4 are connected to the second node 2 (N2) and the cell plate line 8.
The unit cell of the conventional FRAM forms the cell array of FIG. 3. The word lines and plate lines are arranged in parallel in the direction of the row, and the bit lines and/bit lines are arranged in parallel in the direction of the column. Each memory cell is located at the point where each row and each column intersect each other. Access to each memory cell can be performed by selecting both the row and column on which the memory cell is placed.
The operation of the conventional FRAM is described with reference to FIG. 4. A chip enable signal CSBpad is enabled from a level “HIGH” to a level “LOW”, to start decoding of the address signal. A word line driving signal applied to a selected word line transit from a level “LOW” to a level “HIGH” to select a cell. Before the word lines are activated to allow memory cell data to be loaded on corresponding bit line and/bit line, the bit line and/bit line become an equivalent potential of VSS according to a control signal EQ for the equivalent potential.
Thereafter, the word line driving signal is enabled from a level “LOW” to level “HIGH”, to electrically connect the selected memory cell to the bit line and/bit line. Upon connection of the selected memory cell to the bit line and/bit line, a pulse of a level “HIGH” is applied to the plate line P/L, to load the data stored in the ferroelectric capacitor on bit line and/bit line. In this state, a sense amplifier enable signal SAN (for turning on the NMOS transistor of a sense amplifier) transits from a level “LOW” to a level “HIGH”, and a sense amplifier enable signal SAP (for turning on the PMOS transistor of the sense amplifier) transits from a level “HIGH” to a level “LOW”, such that the voltage of the bit line and/bit line is amplified.
To recover the data destroyed during data reading operation, the signal CSBpad is transferred from a level “HIGH” to a level “LOW”, being disabled while the word lines is being activated. The signal CSBpad is disabled from a level “HIGH” to a level “LOW” and the signal applied to the plate line is transferred from a level “HIGH” to a level “LOW”, to restore the data destroyed.
In the conventional FRAM, as described above, the word line and the plate line are separately constructed, to complicate the structure of the memory cell, which increases its area. Thus, the word line and plate line receive control signals different from each other, which creates difficulty in the control of the control signals in the input/output operation of data.